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TDA7342
Digitally controlled audio processor
Features
Input multiplexer - Two stereo and one mono inputs - One quasi differential input - Selectable input gain for optimal adaptation to different sources Fully programmable loudness function Volume control in 0.3dB steps including gain up to 20dB Zero crossing mute, soft mute and direct mute Bass and treble control Four speaker attenuators - Four independent speakers control in 1.25dB steps for balance and fader facilities - Independent mute function All functions programmable via serial I2C bus Due to a highly linear signal processing, using CMOS-switching techniques instead of standard bipolar multipliers, very low distortion and very low noise are obtained. Several new features like softmute, and zero-crossing mute are implemented. The soft Mute function can be activated in two ways: 1. Via serial bus (Mute byte, bit D0) Directly on pin 21 through an I/O line of the microcontroller 2.
LQFP32

Description
The audioprocessor TDA7342 is an upgrade of the TDA731X audioprocessor family.
Very low DC stepping is obtained by use of a BICMOS technology.
Order codes
Part number TDA7342N TDA7342NTR Package LQFP32 LQFP32 Packing Tube Tape and reel
November 2006
Rev 2
1/20
www.st.com 1
Contents
TDA7342
Contents
1 Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
I2C Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 3.4 3.5 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 4.3 4.4 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
TDA7342
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Speaker attenuators (LF, LR, RF, RR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
List of figures
TDA7342
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connections (Top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data validity on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LQFP32 Mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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TDA7342
Block diagram and pin descriptions
1
1.1
Figure 1.
Block diagram and pin descriptions
Block diagram
Block diagram
C17 100nF C11 C13 47nF OUT(L) 16 IN(L) 15 LOUD(L) 9 21 SM BOUT(L) R2 4.7K C18 100nF 32 C19 2.7nF TREBLE(L) SPKR ATT 25 MUTE ZERO CROSS + MUTE L3 23 MUTE CD CD GND C3 10 INPUT SELECTOR + GAIN SOFT MUTE SERIAL BUS DECODER + LATCHES 28 27 26 SPKR ATT R3 M R2 5 8 6 7 R3 24 C8 M R2 R1 ZERO CROSS + MUTE OUT RIGHT FRONT OUT LEFT REAR LOUD+ VOL BASS TREBLE OUT LEFT FRONT
BIN(L) 17
18
C1 LEFT INPUTS C2 C6
L1 L2
13 12 L2 M
L1
SPKR ATT
L3
11
SCL SDA DIGGND BUS
C7
MONO INPUT
LOUD+ VOL
BASS
TREBLE
MUTE
RIGHT INPUTS
C4 C5
R1
SPKR ATT 22 MUTE OUT RIGHT REAR
SUPPLY
30 VS
31
29 CREF 10F C9
3 OUT(R)
2 IN(R)
4 LOUD(R) C12 47nF
14 CSM CSM 47nF
20
19 BOUT(R) C14 100nF R1 4.7K
1 BIN(R) C15 100nF TREBLE(R)
D94AU104B
C10
C16 2.7nF
1.2
Pin description
Figure 2. Pin connections (Top view)
DIG GND OUT LF 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 LOUD L CD GND IN L3 IN L2 IN L1 CSM IN L OUT L CREF TR L GND SDA SCL
32 31 30 29 28 27 26 25 TR R IN R OUT R LOUD R IN R3 IN R2 IN R1 MONO 1 2 3 4 5 6 7 8 OUT RF OUT LR OUT RR SM BOUT R BIN R BOUT L BIN L
VS
D94AU105A
5/20
Electrical specifications
TDA7342
2
2.1
Electrical specifications
Absolute maximum ratings
Table 1.
Symbol VS Tamb Tstg
Absolute maximum ratings
Parameter Operating supply voltage Operating ambient temperature Storage temperature range Value 10.5 -40 to 85 -55 to 150 Unit V C C
Table 2.
Symbol Rth j-amb
Thermal data
Parameter Thermal resistance junction-pins Value 150 Unit C/W
Table 3.
Symbol VS VCL THD S/N SC
Quick reference data
Parameter Supply voltage Max. input signal handling Total harmonic distortion V = 1Vrms f = 1KHz Signal to noise ratio Channel separation Volume control 0.3dB step Treble control 2dB step Bass control 2dB step Fader and balance control 1.25dB step Input gain 3.75dB step Mute attenuation -59.7 -14 -10 -38.75 0 100 Min. 6 2.1 Typ. 9 2.6 0.01 106 100 20 +14 +18 0 11.25 0.08 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB dB
Table 4.
Electrical characteristics (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Parameter Test condition Min. Typ. Max. Unit
Symbol Input selector RI VCL SI RL GI MIN GI MAX
Input resistance Clipping level Input separation Output load resistance Minimum input gain Maximum input gain d 0.3%
70 2.1 80 2 -0.75
100 2.6 100
130
K VRMS dB K
0
0.75
dB dB
10.25 11.25 12.25
6/20
TDA7342 Table 4.
Electrical specifications Electrical characteristics (continued) (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Parameter Step resolution Input noise DC Steps GIINto GIMAX 3 mV 20Hz to 20 KHz unweighted Adjacent gain steps VDC Test condition Min. 2.75 Typ. 3.75 2.3 1.5 10 Max. 4.75 Unit dB V mV
Symbol Gstep
eN
Differential input (IN 3) Input selector BIT D6 = 0 (0dB) RI Input resistance Input selector BIT D6 = 1(6dB) Common mode rejection ratio Distortion Input noise Differential gain D6 = 1 -7 -6 -5 dB VCM = 1VRMS; f =1KHz f = 10KHz VI= 1VRMS 20Hz to 20KHz; Flat; D6 = 0 D6 = 0 GDIFF -1 14 48 45 20 75 70 0.01 5 0 1 0.08 30 K dB dB % V dB 10 15 20 K
CMRR d
eIN
Volume control RI GMAX AMAX ASTEPC ASTEPF EA Et VDC Input resistance Maximum gain Maximum attenuation Step resolution coarse attenuation Step resolution fine attenuation G = 20 to -20dB Attenuation set error G = -20 to -58dB Tracking error Adjacent attenuation Steps DC Steps From 0dB to AMAX 0.5 5 mV -3 0 -3 2 2 3 dB dB mV 35 18.75 57.7 0.5 0.11 -1.25 50 20 59.7 1.25 0.31 0 21.25 62.7 2.0 0.51 1.25 K dB dB dB dB dB
Loudness control RI AMAX Astep Internal resistor Maximum attenuation Step resolution Loud = On 35 17.5 0.5 50 18.75 1.25 65 20.0 2.0 K dB dB
Zero crossing mute
7/20
Electrical specifications Table 4.
TDA7342
Electrical characteristics (continued) (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Parameter Test condition WIN = 11 Min. Typ. 20 40 80 160 80 0dB to Mute 100 0 3 Max. Unit mV mV mV mV dB mV
Symbol
VTH
Zero crossing threshold
(1)
WIN = 10 WIN = 01 WIN = 00
AMUTE VDC Soft mute AMUTE
Mute attenuation DC Step
Mute attenuation CCSM = 22nF; 0 to -20dB; I = IMAX CCSM = 22nF; 0 to -20dB; I = IMIN OFF current Soft mute threshold Pull-up resistor (pin 21) (pin 21) Level high (pin 21) Level low Soft mute active
(2)
45 0.7 20 25
60 1 35 50 1 1.7 55 75
dB ms ms A A 3.5 65 V K V 1 V
TDON
ON Delay time
TDOFF VTHSM RINT VSMH VSML
VCSM= 0V; I = IMAX VCSM= 0V; I = IMIN
1.5 35 3.5
2.5 50
Bass control BBOOST BCUT Astep Rg Max bass boost Max bass cut Step Resolution Internal Feedback Resistance 15 -8.5 1 45 18 -10 2 65 20 -11.5 3 85 dB dB dB K
Treble control CRANGE Astep Control Range Step Resolution 13 1 14 2 15 3 dB dB
Speaker attenuators CRANGE Astep AMUTE EA VDC Control range Step resolution Output mute attenuation Attenuation set error DC Steps Adjacent attenuation steps 0 Data word = XXX11111 35 0.5 80 37.5 1.25 100 1.25 3 40 2.00 dB dB dB dB mV
8/20
TDA7342 Table 4.
Electrical specifications Electrical characteristics (continued) (VS = 9V; RL = 10K; Rg = 50; Tamb = 25C; all gains = 0dB; f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Parameter Test condition Min. Typ. Max. Unit
Symbol Audio output Vclip RL RO VDC General VCC ICC PSRR
Clipping Level Output Load Resistance Output Impedance DC Voltage Level
d = 0.3%
2.1 2
2.6
Vrms K
30 3.5 3.8
100 4.1
V
Supply Voltage Supply Current f = 1KHz Power Supply Rejection Ratio B = 20 to 20kHz "A" weighted Output muted (B = 20 to 20kHz flat)
6 5 60
9 10 80 65 2.5 5 0 0 106
10.2 15
V mA dB dB V
eNO
Output Noise All gains 0dB (B = 20 to 20kHz flat) Total Tracking Error Signal to Noise Ratio Channel Separation Distortion VIN =1V AV= 0 to -20dB AV= -20 to -60dB All Gains = 0dB; VO= 1Vrms 80 15 1 2 V dB dB dB dB 0.08 %
Et S/N SC d
100 0.01
Bus inputs VIL VlN IlN VO Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge VIN = 0.4V IO= 1.6mA 3 -5 0.4 5 0.8 1 V V A V
1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold 2. Internal pull-up resistor to Vs/2; LOW = softmute active
9/20
I2C Bus interface
TDA7342
3
I2C Bus interface
Data transmission from the microprocessor to the TDA7342 and vice versa takes place through the 2 wires of the I2C BUS interface, consisting of the two lines SDA and SCL (pullup resistors to the positive supply voltage must be externally connected).
3.1
Data validity
As shown in fig. 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2
Start and stop conditions
As shown in fig. 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
3.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first.
3.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 6). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledgment after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
3.5
Transmission without acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the microprocessor can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
10/20
TDA7342 Figure 3. Data validity on the I2C BUS
SDA
I2C Bus interface
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 4.
Timing diagram of I2C BUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 5.
Acknowledge on the I2C BUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
11/20
Software specification
TDA7342
4
4.1
Software specification
Interface protocol
The interface protocol comprises:

A start condition (s) A chip address byte, (the LSB bit determines read/write transmission) A subaddress byte. A sequence of data (N-bytes + acknowledge) A stop condition (P) Interface protocol
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB R/W ACK MSB X X X I SUBADDRESS LSB A3 A 2 A1 A 0 ACK MSB DATA DATA 1 ... DATA n LSB ACK P
Figure 6.
D05AU1575
ACK = Acknowledge S = Start P = Stop I = Auto Increment X = Not used Max clock speed 500kbits/s
4.2
Auto increment
If bit I in the subaddress byte is set to "1", the auto increment of the subaddress is enabled Table 5.
MSB X X X I A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0
Subaddress (receive mode)
LSB A0 0 1 0 1 0 1 0 1 0 Input selector Loudness Volume Bass, treble Speaker attenuator LF Speaker attenuator LR Speaker attenuator RF Speaker attenuator RR Mute Function
12/20
TDA7342
Software specification
4.3
Transmitted data
Table 6.
MSB X X X X X SM ZM
Send mode
LSB X
ZM = Zero crossing muted (HIGH active) SM = Soft mute activated (HIGH active) X = Not used
The transmitted data is automatically updated after each ACK. Transmission can be repeated without new chip address.
4.4
Data byte specification
X = not relevant; set to "1" during testing Table 7.
MSB D7 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D6 D5 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1
Input selector
LSB Function D0 0 1 0 1 0 1 0 1 not used IN 2 IN 1 AM mono not used not used not allowed not allowed 11.25dB gain 7.5dB gain 3.75dB gain 0dB gain 0dB differential input gain (IN3) -6dB differential input gain (IN3)
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
13/20
Software specification Table 8.
MSB D7 X X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X X D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1
TDA7342 Loudness
LSB Function D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB -10dB -11.25dB -12.5dB -13.75dB -15dB -16.25dB -17.5dB -18.75dB Loudness OFF (1)
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0 NOTE 1: If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency response. D0 to D3 determine the attenuation level.
Table 9.
MSB D7 D6
Mute
LSB Function D5 D4 D3 D2 D1 D0 1 0 1 1 0 0 1 0 0 0 1 1 0 1 1 Soft mute on Soft mute with fast slope (I = IMAX) Soft mute with slow slope (I = IMIN) Direct mute Zero crossing mute on Zero crossing mute off (delayed until the next zerocrossing) Zero crossing mute and pause detector reset 160mV ZC Window threshold (WIN = 00) 80mV ZC Window threshold (WIN = 01)
14/20
TDA7342 Table 9.
MSB D7 D6 1 1 0 1 D5 0 1 D4 D3 D2 D1
Software specification Mute
LSB Function D0 40mV ZC Window threshold (WIN = 10) 20mV ZC Window threshold (WIN = 11) Non symmetrical bass cut (note 4) Symmetrical bass cut
An additional direct mute function is included in the speaker attenuators.
Note 4: Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
Table 10.
MSB D7
Speaker attenuators (LF, LR, RF, RR)
LSB Function D6 D5 D4 D3 D2 D1 D0 1.25dB step
X X X X X X X X
X X X X X X X X
X X X X X X X X
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0dB -1.25dB -2.5dB -3.75dB -5dB -6.25dB -7.5dB -8.75dB 10dB step
X X X X X
X X X X X
X X X X X
0 0 1 1 1
0 1 0 1 1 1 1 1
0dB -10dB -20dB -30dB Speaker mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0 Table 11.
MSB D7 D6 D5 D4 D3 D2 D1
Bass/Treble
LSB Function D0 Treble step 0 0 0 0 0 0 0 1 -14dB -12dB
15/20
Software specification Table 11.
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 1 1 0 0 1 1 1 1 0 0 1 1 0 0
TDA7342 Bass/Treble (continued)
LSB Function D0 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB Bass steps
0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0
0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0
-10dB -8dB -6dB -4dB -2dB -0dB -0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 146B 18dB
For example 12dB Treble and -8dB Bass give the following data byte: 0 0 1 1 1 0 0 1
16/20
TDA7342
Software specification
Table 12.
MSB D7 D6
Volume
LSB Function D5 D4 D3 D2 D1 D0 0.31db fine attenuation steps 0 0 1 1 0 1 0 1 0db -0.31db -0.62db -0.94db 1.25db coarse attenuation steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0db -1.25db -2.5db -3.75db -5db -6.25db -7.5db -8.75db 10db gain / attenuation steps
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
20db 10db 0db -10db -20db -30db -40db -50db
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1 Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
NB.
Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
17/20
Package information
TDA7342
5
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 7. LQFP32 Mechanical data & package dimensions
mm DIM. MIN. A A1 A2 b c D D1 D3 E E1 E3 e L L1 K ccc 0.450 8.800 6.800 0.050 1.350 0.300 0.090 8.800 6.800 9.000 7.000 5.600 9.000 7.000 5.600 0.800 0.600 1.000 3.500 7.000 0.100 1.400 0.370 TYP. MAX. 1.600 0.150 0.0020 MIN. TYP. MAX. 0.0630 0.0059 inch
OUTLINE AND MECHANICAL DATA
1.450 0.0531 0.0551 0.0571 0.450 0.0118 0.0146 0.0177 0.200 0.0035 0.0079
Weight: 0.20gr
9.200 0.3465 0.3543 0.3622 7.200 0.2677 0.2756 0.2835 0.2205 9.200 0.3465 0.3543 0.3622 7.200 0.2677 0.2756 0.2835 0.2205 0.0315 0.750 0.0177 0.0236 0.0295 0.0394 0.1378 0.2756 0.0039
LQFP32 (7 x 7 x 1.40mm)
0060661 D
18/20
TDA7342
Revision history
6
Revision history
Table 13.
Date 24-Jan-2006 20-Nov-2006
Document revision history
Revision 1 2 Initial release. Update package information, layout changes, text modifications. Changes
19/20
TDA7342
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